1. Field of the Invention
This invention relates to ESD protection circuits and more particularly to designs for minimizing damage at drain contacts around the ends of the MOS multiple fingers.
2. Description of Related Art
In the design of ESD protection circuits, grounded-gate MOS devices are usually used as the ESD protection devices to bypass the ESD current when ESD overstress is applied to the I/O pins of an IC. For sustaining a large ESD current the channel width of the protection MOS transistor should be large enough. With a large device dimension, the ESD MOS transistors are traditionally implemented with multiple fingers to bypass the ESD current efficiently.
However ESD damaged areas caused by contact spiking are often located at the drain contacts around the two ends of the multiple drain fingers is more serious in machine model ESD tests due to the faster rise time and the larger current of the ESD pulse.
A schematic diagram of a popular input ESD protection circuit is shown in FIG. 1, which is used to bypass the ESD overstress from the I/O pins to VDD/VSS power rails. In this design, a PMOS transistor (Mp) with large channel width is connected between the VDD power rail and the PAD. The gate of the PMOS transistor is connected to VDD power rail through a resistor Rp. PMOS transistor Mp is turned off during the normal operating condition. Resistor Rp is used to prevent the gate oxide breakdown of transistor Mp in an ESD overstress condition. The parasitic lateral p-n-p Bipolar Junction Transistor (BJT) of transistor Mp is also shown in FIG. 1. The source and drain P+ diffusions of transistor Mp are the emitter and collector of the BJT, respectively. The base of the BJT is formed by the N-well and is connected to VDD power line through the parasitic N-well resistance Rw. The parasitic lateral p-n-p BJT is used to bypass the ESD current when ESD overstress is across PAD and VDD node. An NMOS transistor (MN) with large channel width is used to bypass the ESD current when ESD overstress is across PAD and VSS node. The gate of the NMOS transistor is connected to VSS power rail through a resistor RN. MN is turned off during the normal operating condition. RN is used to prevent the gate oxide breakdown of MN in ESD overstress condition. The parasitic lateral n-p-n BJT of MN is shown in the figure, too. The source and drain N+ diffusions of MN are the emitter and collector of the BJT, respectively. The base of the BJT is formed by the p-substrate and is connected to VSS power line through the parasitic substrate resistance Rsub.
For implementing the PMOS transistor Mp and NMOS transistor MN in FIG. 1 with large channel width, the multiple-finger layout style is usually applied in such ESD protection devices.
The multiple-finger layout style of an ESD-protection NMOS transistor device is drawn in FIG. 2. The parameters of layout geometry should be designed appropriately to improve the ESD level of ESD-protection device. For example, the distance of drain contact to polysilicon-gate edge and the distance of source contact to polysilicon-gate edge are two important layout parameters.
These two parameters are termed as xe2x80x98dxe2x80x99 and xe2x80x98sxe2x80x99 in FIG. 2, respectively. The symmetric layout on the multiple fingers of the MOS transistor is very important for the turn-on uniformity of these fingers during ESD stress.
Recently, there were several layout approaches proposed to improve the ESD robustness of the ESD-protection devices [1-8]. Different layout styles of a same ESD-protection device will perform different ESD robustness. The ESD performance is very strongly dependent on layout. Therefore, improving ESD performance through appropriate layout style is very important for ESD design. FIG. 3 is a layout technique reported in [2] [4] to improve the ESD robustness of the ESD-protection device. In this implementation, the P+ pick-up with contacts are inserted between the source sides of two neighboring NMOS transistor fingers. These P+ pick-up are connected to VSS power rail through the contacts. In this implementation, the substrate resistance, Rsub, of each MOS transistor finger is nearly the same, therefore the turn-on uniformity among the MOS multiple fingers can be improved. This is an example of improving ESD performance by layout technique.
But, there are still some problems in the traditional multiple-finger layout style. The traditional finger-type layout for NMOS is illustrated in FIG. 2. Its cross-sectional view along the line 4-4xe2x80x2 in FIG. 2 is shown in FIG. 4, which is demonstrated in a p-substrate bulk CMOS process. There are two important ESD-related spacings in this traditional finger-type layout, which are xe2x80x98dxe2x80x99 and xe2x80x98sxe2x80x99 as we mentioned previously.
Except these two parameters, another important ESD-related spacing, denoted as xe2x80x98G0xe2x80x99 in FIG. 2, often degrades ESD robustness of CMOS I/O circuits.
FIG. 5 is a schematic cross-sectional view along the line 5-5xe2x80x2 in FIG. 2 prior art device showing the ESD peak-discharging effect of the finger""s end of the finger-type layout. FIG. 5 includes a plot for explaining the xe2x80x98G0xe2x80x99 spacing. In FIG. 5, there exists a parasitic diode D1, between the P+ diffusion and the N+ diffusion of the drain. The spacing from the edge of p+ diffusion to the edge of drain N+ diffusion is termed as xe2x80x98G0xe2x80x99. If this spacing is smaller than that from the drain contact to its source contact, the diode D1 will be first broken down due to the ESD peak-discharging effect before the NMOS drain is broken down. Even if the spacing xe2x80x98G0xe2x80x99 is larger than the spacing xe2x80x98dxe2x80x99 in the finger-type NMOS device, the ESD hot spot may still occurs at the drain edge due to the peak structure at the end of the finger of the finger-type layout. This phenomenon occurs often in the machine-model (MM) ESD test. The machine-model ESD stress of 200V has a higher and faster ESD current than that of the human-body-model (HBM) ESD stress of 2000V. In the fast ESD transition, not only the spacing effect but also the peak-discharging effect can cause the ESD damage located on the end of the drain finger.
For solving the problems of finger-type layout mentioned above, some other different layout styles of the ESD protection device were proposed to improve the ESD robustness [6-8]. The square-type [6], hexagon-type [7], and octagonal-type [8] layouts were used to drawn the ESD protection devices. The square-type layout style, which is used to realize the MOS device [6], is plotted in FIG. 6. In FIG. 6, there are four small-dimension square cells to form a large-dimension NMOS device. The polysilicon gate in each square cell is drawn in a square ring. The contacts at the source region are placed in a square-type arrangement. Outside the NMOS device, there are double guard rings. All the layout elements in a square cell, including the contacts, have to be placed as symmetrically as possible to ensure uniform ESD current flow in the NMOS device to increase its ESD reliability. By using the square-type layout design, there is no xe2x80x98G0xe2x80x99 spacing in the square-type output transistors. Moreover, no parasitic diode directly closes to the drain edge in the square-type layout, so the ESD robustness of output transistors is not degraded by the ESD peak-discharging effect as shown in FIG. 5 with the traditional finger-type layout. By the square-type layout proposed in [6], the layout area of CMOS output transistors can be effectively reduced but the driving capability is higher and the ESD reliability is better. Because the output transistors realized by more symmetrical device structures, the transistors can be more uniformly triggered during the ESD-stress events. This is another example of improving ESD robustness by modifying layout style of the ESD protection device.
Although some approaches had been proposed to improve the turn-on uniformity of different MOS fingers, the uniformity problem exists in a single MOS finger. FIG. 7 shows the parasitic lateral n-p-n BJT devices of the multiple-finger NMOS transistors. The lateral n-p-n BJT of each NMOS transistor finger can be viewed as the combination of several parallel lateral n-p-n BJT devices, Q1, . . . , Qj,. . . , and QN, which is shown in FIG. 7. N is the number of drain contacts in single column in the layout. Q1 and QN are the BJT devices at the two ends of the polysilicon-gate. For each BJT, the base of the BJT is connected to ground through the substrate resistors. Bases of Q1, Qj, and QN are connected to ground through R1, Rj, and RN, respectively. For the layout style shown in FIG. 7, the characteristics of Q1, Qj, and QN are not the same to each other. There exist peak structures in Q1 and QN in the traditional finger-type layout, which is demonstrated in FIG. 5. The ESD peak-discharging effect can degrade the ESD robustness of the finger-type MOS transistors. Therefore, ESD damages are often found at the end of the finger, which are shown in FIG. 7. This is the non-uniformity problem existing within one finger of MOS transistor. The damage at the ends of the finger degrades its ESD level in the machine model ESD test. The rise time of the machine model ESD event is much faster than that of the human body model, and the current of machine model ESD event is larger than that of human body model. Before the other BJT devices are turned on, the ESD damages at the end of the finger have occurred.
The illustration of the peak-discharging effect on the finger-type MOS transistor is shown in FIG. 8. The distribution of the ESD current path is shown in this figure. For the positions of xe2x80x98axe2x80x99, xe2x80x98bxe2x80x99, xe2x80x98cxe2x80x99, and xe2x80x98dxe2x80x99, the current paths are different from others. They have more current paths and therefore the induced substrate current is more than that of others. The parasitic BJT devices at these positions will be triggered on faster than others. In deep-submicron CMOS technology, a lot of damage samples were found at the ends of the MOS finger after MM ESD test. Therefore, the non-uniformity problem in a single MOS finger causes the degradation on its ESD robustness, even if the MOS has a large device dimension.
Patents cited below describe the features as follows: a method [1] of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuits; source contact placement [2] for efficient ESD/EOS protection in grounded substrate MOS integrated circuit; an ESD protection circuit [3] employing a lateral NPN transistor to provide a low resistance discharge path for ESD currents; a layout [4] for an ESD input-protection circuit; a multi-finger MOS transistor element [5] where all base resistances of each finger are equal; an ESD device [6] having a square layout style to realize the MOS device; a hexagonally shaped CMOS device [7] constructed for an ESD protection device; an N-sided polygonal cell layout [8] for a multiple cell transistor constructed for use in an ESD protection circuit; an ESD protection circuit [9] for use with mixed voltages in integrated circuits. Several publications [10, 11, 12] discuss the layout of CMOS transistors to provide uniform current density in high current applications such as ESD events.
[1] C. H. Diaz, C. Duvvury, and S.-M. Kang, xe2x80x9cMethod of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit,xe2x80x9d U.S. Pat. No. 5,468,667, 1995.
[2] C. H. Diaz, C. Duvvury, and S.-M. Kang, xe2x80x9cSource contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit,xe2x80x9d U.S. Pat. No. 5,404,041, 1995.
[3] T. C. Chen, and D. S. Culver, xe2x80x9cESD protection circuit,xe2x80x9d U.S. Pat. No. 5,329,143, 1994.
[4] J.-H. Lee, xe2x80x9cLayout of ESD input-protection circuit,xe2x80x9d U.S. Pat. No. 5,811,856, 1998.
[5] T.-L. Yu, and K. Young, xe2x80x9cMulti-finger MOS transistor element,xe2x80x9d U.S. Pat. No. 5,831,316, 1998.
[6] M.-D. Ker, C.-Y. Wu, C.-C. Huang, C.-N. Wu, and T.-L. Yu, xe2x80x9cElectrostatic discharge protection device,xe2x80x9d U.S. Pat. No. 5,714,784, 1998.
[7] M.-D. Ker, C.-Y. Wu, C.-C. Huang, C.-N. Wu, and T.-L. Yu, xe2x80x9cHexagon CMOS device,xe2x80x9d U.S. Pat. No. 5,838,050, 1998.
[8] M.-D. Ker, T.-S. Wu, and K.-F. Wang, xe2x80x9cN-sided polygonal cell layout for multiple cell transistor,xe2x80x9d U.S. Pat. No. 5,852,315, 1998.
[9] H. P. Nguyen and J. D. Walker, xe2x80x9cElectrostatic Discharge Protection System for Mixed Voltage Application Specific Integrated Circuit Designxe2x80x9d, U.S. Pat. No. 5,616,943, 1997.
[10] xe2x80x9cArea-Efficient Layout Design for CMOS Output Transistorsxe2x80x9d, M.-D. Ker, C.-Y. Wu, and T.-S. Wu, IEEE Transactions On Electron Devices, VOL. 44, NO.4, APRIL 1997, pp. 635-645.
[11] xe2x80x9cESD Protection for Output Pad with Well-Coupled Field-Oxide Device in 0.5-pm CMOS Technologyxe2x80x9d, C.-N. Wu, and M.-D. Ker, IEEE Transactions on Electron Devices, VOL. 44, NO.3, MARCH 1997, pp. 503-505.
[12] xe2x80x9cThe Behavior of Very High Current Density Power MOSFET""sxe2x80x9d, G. Evans and G. Amaratunga, IEEE Transactions On Electron Devices, VOL. 44, NO.7, JULY 1997, pp. 1148-1153.
In accordance with this invention, a new layout style is employed to reduce the probability of damage at drain contacts around the ends of the MOS multiple fingers. Therefore the layout area can be more compact to save silicon cost.
By applying this invention on the layout of ESD protection circuit, the ESD level can be improved significantly, especially in the machine model ESD event.
In this invention, the ESD protection circuit with a novel layout style improves the turn-on uniformity of MOS transistor finger. By improving the turn-on uniformity of the MOS transistor finger, the ESD robustness of the ESD protection circuit can be improved. The layout style and application of this invention in the 3V/5V tolerant I/O circuits are also presented in this document.
A method in accordance with this invention comprises forming a layout for ESD-protection MOS transistors including forming gate electrodes of the ESD-protection MOS transistors which are formed with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity. Alternatively the ESD-protection MOS transistors are formed with asymmetric wider ends at the periphery of the active region whereby the transistors have improved turn-on uniformity.
Preferably, the ESD protection transistors are NMOS and PMOS.
Preferably, source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.
Preferably, the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.
Preferably, the modified layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the top device.
A layout of ESD-protection MOS transistors in accordance with another aspect of this invention,comprises gate electrodes of the ESD-protection MOS transistors being formed with wider ends or alternatively with asymmetric wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.
Preferably, the ESD protection transistors are NMOS and PMOS.
Preferably, source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.
Preferably, the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.
Preferably, the layout style is provided for stacked NMOS and PMOS devices in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the top device.